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4.5
Exception Handling
The following sections describe the conditions and the device response for each detectable exception. In the event that mul-
tiple exceptions exist, the exception response is determined by the priority listed in Table 33 .
Table 33. SPI Error Response Priority
Effect on Data
Error Priority
Exception
SPI Data
Arming Output
PCM Output
1
2
3
4
5
6
7
8
SPI Error
SPI MISO Error
Invalid Request
DEVINIT Bit Set
DEVRES Error
CRC Error
Self Test Error
Offset Monitor Error
Error Response
Error Response
Error Response
Error Response
Error Response
Error Response
Error Response
Error Response
No Update
No Update
No Update
No Update
No Update
No Update
No Update
No Update
No Effect
No Effect
No Effect
Disabled
Disabled
No Effect
No Effect
No Effect
4.5.1
SPI Error
The following SPI conditions result in a SPI error:
? SCLK is high when CS is asserted
? The number of SCLK rising edges detected while CS is asserted is not equal to 16
? SCLK is high when CS is negated
? Command message parity error (MOSI)
? Bit 15 of Acceleration Data Request is not equal to ‘0’
? Bits 4 through 11 of an Acceleration Request are not equal to ‘0’
? Bits 3 of an Acceleration Request is not equal to ‘1’
? Bits 0 through 7 of a Register Read Request are not equal to ‘0’
The device responds to a SPI error with a “SPI Error” response as shown in Table 30 . This applies to both acceleration data
request SPI errors, and Register Access SPI errors.
The arming function will not be updated if a SPI Error is detected. The PCM output is not affected by a SPI Error.
MMA65xx
Sensor
50
Freescale Semiconductor, Inc.
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